Many mobile computing devices, such as laptops, personal digital assistants, cellular telephones, and the like, attempt to provide long lasting performance through the conservation of battery life. One way of extending battery life is to temporarily reduce the power that is consumed by such devices. The total amount of power that a device consumes is determined by the individual power demands of device components. For example, the central processing unit (CPU), high speed bus interface, and low speed bus interface all have individual power demands.
Techniques for reducing power consumption of electronic devices include resource hibernation. Resource hibernation allows particular components of an electronic device to be powered down, placed into a “sleep mode” or otherwise placed in a lower power consumption mode during periods of inactivity. The Advanced Configuration and Power Interface (ACPI) specification [see e.g. ADVANCED CONFIGURATION AND POWER INTERFACE SPECIFICATION Revision 3.0a, Dec. 30, 2005, the contents of which are hereby incorporated by reference] for example, defines a number of different device power states that may be used to reduce the overall power consumed.
A number of processor power states are defined by the ACPI specification (for example, C0, C1, C2, and C3). Each power state corresponds to a particular level of power consumption. In general, for a given power state, along with a greater savings in power there is associated a greater latency period for entering and exiting the power state.
The C0 power state is an active power state in which the processor is in working mode and executes instructions. The C1 power state is a halt state that puts the processor in a non-executing state, offering greater power conservation than the C0 state. The C2 and C3 power states are “sleep” states with further improved power savings. For example, in the C2 and C3 power states, significant portions of the high speed bus interface (often also referred to as “northbridge”), may be powered down to save power.
It is possible to power down significant portions of the high speed bus interface while the processor is in a C2 or C3 power state because the high speed bus interface does not need to handle any new processor requests while the processor is its “sleep” state. Furthermore, control signals signal when the processor is transitioning from its sleep state to enter an active state, giving the high speed bus interface sufficient time to power up to process new processor requests.
While more advanced power saving states such as C2 and C3 provide greater power savings, there is a high latency involved in entering and exiting these states. Processors will only be placed in a C2 or C3 state if the processor has been idle for a sufficiently long period of time (e.g. in the order of hundreds of microseconds, which, for a typical 5 ns processor bus clock, is in the order of hundreds of thousands of clock cycles). Thus, the high speed bus interface generally remains in a high power consumption mode during shorter periods of processor idle time that are not long enough to trigger entrance into sleep states such as C2 and C3.
In view of the foregoing, there remains a need for methods that lower the power consumption associated with processor data buses and chipsets.